CEDS

ANX2166

Timing Controller
Timing Controller
4-Lane eDP TCON with PSR2
Overview: 

The ANX2166 is an eDP 1.4b compliant TCON supporting Panel Self Refresh (PSR) and Selective Update PSR (PSR2) functions.

The ANX2166 features RapidLink™ and QuietLink™. The RapidLink feature allows for instantaneous clock recovery for no-link training wake-up and the QuietLink feature reduces DisplayPort™ (DP) voltage swing, which helps reducing power consumption.

The ANX2166 adopts the Analogix-patented low power technology of Gapless architecture.

ANX2166 can be adopted by Intel, AMD, Qualcomm, MTK platform designs.

Main Features: 
  • Resolution supported:
    • 3240x2160 10bpc @120Hz
    • 2880x1920 10bpc @144Hz
    • 2736x1824 10bpc @144Hz
    • 2496x1664 10bpc @144Hz
    • 2256x1504 10bpc @144Hz
    • 1920x1080 10bpc @240Hz
  • Color depth supported:
    • input 6/8/10bpc
    • output 6/8bpc, with 8+2 FRC
  • eDP receiver
    • Compliant with DisplayPort standard v1.3 and eDP standard v1.4b
    • Up to four lanes at 8.1Gbps
    • Support multi-link rate 8.1Gbps, 5.4Gbps, 4.32Gbps, 3.24Gbps, 2.7Gbps, 2.43Gbps, 2.16Gbps, 1.62Gbps
    • Down-spread spectrum (0.5% down spread)
  • P2P interface
  • iSP, CEDS and CEDS+ are supported
  • Up to 16 lanes to 2.6Gbps, with 1D/1C, 2D/1C and 4D/1C
  • P2P PHY output swing level control
  • TCON function
    • GD-IC /GIP/Overlap driving/Multi driving/4,6,8 phase simple GIP flexible gate timing through GPIO, configurable by register
    • Power-on gate output masking to avoid DC/DC over-loading
    • Programmable Fail-safe mode control
  • HDR400 supported with global dimming
  • Power supply: 1.8V/0.9V (3.3V generated internally for HPD output)
  • Package: 7x16 112-pin BGA; package size: 5.0×11×0.82mm (W×L×H)

eDP

ANX2403

Timing Controller
Timing Controller
ANX2403 FullHD eDP1.4 TCON with In-cell Touch
Overview: 

ANX2403 is the world’s lowest power two-lane embedded DisplayPort™ (eDP) 1.4 compliant TCON with Panel Self Refresh (PSR) and Selective update PSR (PSR2) functions. ANX2403 supports Microsoft and Wacom in-cell pen and finger touch functions. It also supports Intel HDR400, which meets ST.2084 and BT.2020 standards.

Main Features: 
Other key features

Features

eDP receiver

  • Integrated high-speed DP-Rx compliant with DisplayPort standard eDP v1.4
  • Up to 2 lanes @2.7Gbps, 2.16Gbps, 2.43Gbps and 1.62Gbps
  • PSR/MBO/PSR2 function through built-in SRAM Source IC interface: CEDS/iSP/EPI/ATPI
  • Up to 12 pairs to support 6-channel 2D/1C or 12-channel 1D/1C configuration
  • CEDS/iSP/EPI/ATPI transmitter up to 2.0Gbps configuration
  • Various swap modes: inter-port swap, intra-port swap, p/n swap, RGB swap, odd/even pixel swap, etc.
  • Scan direction swap
  • Supports Z-inversion (column inversion), and N-line inversion
  • Dual gate mode combined with Z-inversion and non-Z inversion mode
  • CEDS/iSP/EPI/ATPI test pattern mode TCON functions
  • HD (1366x768), HD+ (1600x900), FHD (1920x1080), 1920x1280
  • eDP TCON color depth: 18/24bpp input (30bpp input for HDR), 18/24bpp output
  • Programmable fail-safe mode control
  • Configurable BIST pattern
  • 10-bit Gamma correction table for each color
  • Multiple FRC pattern configurations
  • 8bit->6bit, 9bit->6bit, 10bit->8bit and 10bit->6bit FRC modes
  • 0-D dimming control (DBC) function for backlight low power
  • Color-engine for hue and saturation control
  • LCD overdrive to reduce motion blur in high-performance mode
  • Direct drive G-sync, Free sync, and Adaptive sync
  • eDP sDRRS power saving function
  • Splash-screen feature
  • In-cell Touch function combined with PSR
  • Microsoft/Wacom In-cell timing requirement On-chip SSCG
  • CEDS/EPI/iSP/ATPI 1.6G <Fceds ≤2G (Max. +/-0.5% with 0.25% step, 10/20/30/40KHz, center spreading)
  • CEDS/EPI/iSP/ATPI Fceds≤1.6G (Max. +/-1% with 0.25% step, 10/20/30/40KHz, center spreading)

Intel HDR400

  • EOTF ST.2084 Decoder
  • BT.2020 to sRGB color space mapping
  • 10-bit input and 8-bit output
  • DPCD handshake

Pattern detection

EEPROM shared for EDID and configuration

In-cell touch support for Microsoft and Wacom

PWM generator, PWM pass-through and PWM product modes

TSMC 28nm HPC+ process

Lowest power from 60mW to 80mW (depending on whether PSR is on or off)

Applications: 

显示屏/面板

Package: 
  • Package: BGA-91 (5x9mm), LGA-74 (5x12mm)
Power Requirements: 

Power supply: 1.8V/0.9V (internal 3.3V for HPD)

Detailed Product Information: 

eDP

ANX2433

Timing Controller
Timing Controller
ANX2433 FullHD eDP1.4b PSR1 TCON
Overview: 

ANX2433 is a low power consumption two-lane embedded DisplayPort™ (eDP) 1.4b compliant TCON with PSR  function. It features intermediate link rates (that is, 1.62 (RBR), 2.16, 2.43, and 2.70(HBR)) and reduced voltage  swing. ANX2433 supports Media Buffer Optimization (MBO). It also supports in-cell touch and output to the  CEDS Source Driver Interface.

The PSR feature enables system-level power savings when the displayed image remains static for multiple  display frames. With this feature enabled and the same image displayed spanning across multiple frames, the  ANX2433 stores the image in its DRAM and displays this image from its internal frame buffer, while the eDP  main link may be turned off. Other source functions are also powered down for further power savings.

Main Features: 
Other Features

 

  • eDP receiver
    • Integrated high-speed DP-Rx compliant with  DisplayPort standard eDP v1.4b
    • Up to 2 lanes @2.7Gbps, 2.16Gbps, 2.43Gbps  and 1.62Gbps
    • Normal/Fast/No link training
    • Support PSR1 function by MCP(multi chip  package) DRAM die
    • Supports DRRS/NvDPS/SDRRS functions
    • Supports MBO
  • CEDS protocol, which supports the following:
    • Up to 12-channels
    • CEDS transmitter up to 2.0Gbps configuration
    • Various swap modes: inter-port swap, intra-  port swap, p/n swap, RGB swap, odd/even  pixel swap, etc.
    • Scan direction swap
    • Supports VBPR function
    • Supports Z-inversion(column inversion), and N-  line inversion
    • Programmable charger share control including  disable
  • System IO functions with non-standard  applications
    • EDID access through AUX channel
    • EDID and configuration content check-sum  support
    • On-chip filtered reset
    • EEPROM shared for EDID and configuration  power requirements
    • On-chip SSCG (max. +/-1% with 0.25% step,  10/20/30/40 kHz, center spreading)
  • TCON functions supported
    • HD(1366x768), HD+(1600x900),  FHD(1920x1080), 1920x1280
    • eDP TCON color depth: 18/24bpp input,  18/24bpp output
    • Gate D-IC/GIP timing through GPIO
    • Power-up gate output masking to avoid DC/DC  over-loading
    • Programmable Fail Safe mode control
    • Configurable BIST pattern
    • 10-bit gamma correction table for each color
    • FRC and various FRC pattern configurations
    • PWM generator, PWM pass-through, and PWM  product modes
    • DELL DBC
    • Adaptive sync, Direct drive G-sync support
  • No external crystal required
  • Reduced WWAN interference (SSC on LC clock and  DDR)
  • UMC 55nm SP process
  • Power supply: 1.8V/1.0V (Internal 3.3V HPD)
  • BGA 80 (5x8), pitch 0.65mm
  • RoHS compliant and Halogen free package
Applications: 

显示屏/面板

Detailed Product Information: 

eDP