ANX2403 is the world’s lowest power two-lane embedded DisplayPort™ (eDP) 1.4 compliant TCON with Panel Self Refresh (PSR) and Selective update PSR (PSR2) functions. ANX2403 supports Microsoft and Wacom in-cell pen and finger touch functions. It also supports Intel HDR400, which meets ST.2084 and BT.2020 standards.
Main Features:
Other key features
Features
eDP receiver
Integrated high-speed DP-Rx compliant with DisplayPort standard eDP v1.4
Up to 2 lanes @2.7Gbps, 2.16Gbps, 2.43Gbps and 1.62Gbps
PSR/MBO/PSR2 function through built-in SRAM Source IC interface: CEDS/iSP/EPI/ATPI
Up to 12 pairs to support 6-channel 2D/1C or 12-channel 1D/1C configuration
CEDS/iSP/EPI/ATPI transmitter up to 2.0Gbps configuration
Various swap modes: inter-port swap, intra-port swap, p/n swap, RGB swap, odd/even pixel swap, etc.
Scan direction swap
Supports Z-inversion (column inversion), and N-line inversion
Dual gate mode combined with Z-inversion and non-Z inversion mode
CEDS/iSP/EPI/ATPI test pattern mode TCON functions
HD (1366x768), HD+ (1600x900), FHD (1920x1080), 1920x1280
eDP TCON color depth: 18/24bpp input (30bpp input for HDR), 18/24bpp output
Programmable fail-safe mode control
Configurable BIST pattern
10-bit Gamma correction table for each color
Multiple FRC pattern configurations
8bit->6bit, 9bit->6bit, 10bit->8bit and 10bit->6bit FRC modes
0-D dimming control (DBC) function for backlight low power
Color-engine for hue and saturation control
LCD overdrive to reduce motion blur in high-performance mode
ANX2433 is a low power consumption two-lane embedded DisplayPort™ (eDP) 1.4b compliant TCON with PSR function. It features intermediate link rates (that is, 1.62 (RBR), 2.16, 2.43, and 2.70(HBR)) and reduced voltage swing. ANX2433 supports Media Buffer Optimization (MBO). It also supports in-cell touch and output to the CEDS Source Driver Interface.
The PSR feature enables system-level power savings when the displayed image remains static for multiple display frames. With this feature enabled and the same image displayed spanning across multiple frames, the ANX2433 stores the image in its DRAM and displays this image from its internal frame buffer, while the eDP main link may be turned off. Other source functions are also powered down for further power savings.
Main Features:
Other Features
eDP receiver
Integrated high-speed DP-Rx compliant with DisplayPort standard eDP v1.4b
Up to 2 lanes @2.7Gbps, 2.16Gbps, 2.43Gbps and 1.62Gbps
Normal/Fast/No link training
Support PSR1 function by MCP(multi chip package) DRAM die
Supports DRRS/NvDPS/SDRRS functions
Supports MBO
CEDS protocol, which supports the following:
Up to 12-channels
CEDS transmitter up to 2.0Gbps configuration
Various swap modes: inter-port swap, intra- port swap, p/n swap, RGB swap, odd/even pixel swap, etc.
Scan direction swap
Supports VBPR function
Supports Z-inversion(column inversion), and N- line inversion
Programmable charger share control including disable
System IO functions with non-standard applications
EDID access through AUX channel
EDID and configuration content check-sum support
On-chip filtered reset
EEPROM shared for EDID and configuration power requirements
On-chip SSCG (max. +/-1% with 0.25% step, 10/20/30/40 kHz, center spreading)
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